A charge coupled device (CCD) is usually used as an image-picking device, and has an advantage over an image pickup tube. The advantage is compact, lightweight, low power consumption, and highly reliable. CCD has further advantages of no distortion and no sticking. Therefore, CCD is used for consumer camcorders at a first stage. In recent years, CCD is in general used for various kinds of cameras up to broadcast cameras to which a high visual quality is required.
In fact, when the resolution of a camera is getting higher, problems like a decrease in sensitivity and a decrease in a dynamic range are coming up because an amount of a signal charge of CCD decreases. For solving such problems and getting high quality images with high resolution, noise reduction is absolutely required. Dominant noises generated in CCD are a reset noise which has a correlation with a noise content in a feedthrough-level period and a signal-level period, and a 1/f noise whose level is in inverse proportion to a frequency. The feedthrough-level period and the signal-level period appear in the output of CCD repeatedly.
Various noise reduction methods have been proposed to reduce these noises. One of these is a delay and differential noise suppression method which is described in Japanese Patent Number H5-9987. A gate circuit used in this method has a little lower frequency noise, which is bounced from higher frequency noise. Therefore, this method is highly effective to reduce noise. Japanese Patent Publication Number H4-159880 describes another method for noise reduction, in which non-additive mixing (NAM) circuit is used.
FIG. 8 is a block diagram illustrating a noise reduction circuit employed in a delay and differential noise suppression method of the prior art. The noise reduction circuit is configured as follows. An output terminal of CCD 50 is connected to a non-inverting input terminal (+) of difference circuit 56 and an input terminal of delay circuit 54. An output terminal of delay circuit 54 is connected to an inverting input terminal (−) of difference circuit 56. An output terminal of difference circuit 56 is connected to an input terminal of gate circuit 58, and an output terminal of pulse generator 55 is connected to a control input terminal of gate circuit 58. An output terminal of gate circuit 58 is connected to an input terminal of low pass filter (LPF) 57.
FIG. 9 is a timing chart illustrating an operation of the noise reduction circuit of FIG. 8, namely, waveforms of signals Xa through Xf in FIG. 8.
FIG. 9(a) illustrates a waveform of CCD output signal Xa from CCD 50. In CCD output signal Xa, reset-level period r, feedthrough-level period t, and signal-level period v appear in this order repeatedly. In CCD output signal Xa, a noise Nt in feedthrough-level period t has a correlation with a noise Nv in signal-level period v.
Delay circuit 54 receives CCD output signal Xa from CCD 50, delays signal Xa by specified delay time τ, and outputs delay signal Xb shown in FIG. 9(b) to difference circuit 56. Delay time τ is set so that signal-level time V of CCD output signal Xa overlaps with feedthrough-level period t of delay signal Xb.
CCD output signal Xa of CCD 50 is input to the non-inverting input terminal (+) of difference circuit 56, and delay signal Xb from delay circuit 54 is input to the inverting input terminal (−) of difference circuit 56. Difference circuit 56 calculates a difference (Xa−Xb) between the both input signals, and outputs difference signal Xc of the calculation result shown in FIG. 9(c).
In difference signal Xc, During period v′ which is a part of signal-level period v of CCD output signal Xa shown in FIG. 9(a), noise Nv in signal-level period v and noise Nt in feedthrough-level period t, as they correlate each other, cancel each other and are eliminated.
FIG. 9(d) illustrates a waveform of pulse signal Xd which is output from pulse generator 55 to gate circuit 58. Pulse signal Xd having the same period that CCD output signal Xa has is at a high level only during period v′ in difference signal Xc.
FIG. 9(e) illustrates a waveform of output signal Xe of gate circuit 58. When pulse signal Xd is at high level during period v′ and gate circuit 58 is opened, difference signal Xc is output during period v′. During period v′, difference signal Xc does not have a noise, therefore, output signal Xe of gate circuit 58 does not have a noise.
LPF 57 receives output signal Xe of gate circuit 58, rejects useless high frequencies, makes the signal smoothed, and outputs final output signal Xf shown in FIG. 9(f).
FIG. 10 is a block diagram illustrating a noise reduction circuit in which non-additive mixing (NAM) circuit is employed. An output terminal of CCD 60 is connected to a non-inverting input terminal (+) of difference circuit 66 and an input terminal of first delay circuit 64A. An output terminal of first delay circuit 64A is connected to an inverting input terminal (−) of difference circuit 66. An output terminal of difference circuit 66 is connected to one input terminal of first NAM circuit 61, and an output terminal of pulse generator 65 is connected to another input terminal of first NAM circuit 61. An output terminal of first NAM circuit 61 is connected to an input terminal of second delay circuit 64B and one input terminal of second NAM circuit 62. An output terminal of second delay circuit 64B is connected to another input terminal of second NAM circuit 62. An output terminal of second NAM circuit 62 is connected to an input terminal of low pass filter (LPF) 67.
FIG. 11 is a timing chart illustrating an operation of the noise reduction circuit of FIG. 10, namely, waveforms of signals Ya through Yf in FIG. 10.
FIG. 11(a) illustrates a waveform of CCD output signal Ya of CCD 60. In CCD output signal Ya, reset-level period r, feedthrough-level period t, and signal-level period v appear in this order repeatedly. In CCD output signal Ya, noise Nt in feedthrough-level period t correlates with noise Nv in signal-level period v.
First delay circuit 64A receives CCD output signal Ya, delays signal Ya by specified delay time τ, and outputs delay signal Yb shown in FIG. 11(b) to difference circuit 66. Delay time τ is set so that signal-level period v of CCD output signal Ya overlaps with feedthrough-level period t of delay signal Yb.
CCD output signal Ya is input to the non-inverting input terminal (+) of difference circuit 66, and delay signal Yb of first delay circuit 64A is input to inverting input terminal (−) of difference circuit 66. Difference circuit 66 calculates a difference (Ya−Yb) between the both input signals, and outputs difference signal Yc of the calculation result shown in FIG. 11(c). Difference signal Yc from difference circuit 66 has the same appearance that the difference signal in FIG. 9(c) has. During period v′ of a part of signal-level period v of CCD output signal Ya shown in FIG. 11(a), noise Nv in signal-level period v and noise Nt in feedthrough-level period t, which correlate each other, cancel each other and are eliminated.
FIG. 11(d) illustrates a waveform of pulse signal Yd which is output from pulse generator 65 to gate circuit 61. Pulse signal Yd having the same period that CCD output signal Ya has is at a high level during a period except period v′.
Peak-to-peak value B′ of pulse signal Yd must be larger than peak-to-peak value A′ of difference signal Yc. Since peak-to-peak value A′ is twice as large as peak-to-peak value A, peak-to-peak value B′ is set to a larger value than what is twice as large as peak-to-peak value A of CCD output signal Ya. Therefore, the high level of pulse signal Yd is higher than a highest one of difference signal Yc, and the low level of pulse signal Yd is lower than a lowest one of difference signal Yc.
With difference signal Yc and pulse signal Yd input, first NAM circuit 61 selects a higher level signal between difference signal Yc and pulse signal Yd during any of reset-level period r, feedthrough-level period t, and signal-level period v of CCD output signal Ya. Therefore, mixed signal Ye, which first NAM circuit 61 outputs, has a waveform shown in FIG. 11(e). A waveform of mixed signal Ye is the same as that of difference signal Yc shown in FIG. 11(c) during a period v′, which is a part of signal-level period v of CCD output signal Ya shown in FIG. 11(a). Except during period v′, the waveform of signal Ye is replaced with pulse signal Yd shown in FIG. 11(d). Mixed signal Ye, which first NAM circuit 61 outputs, is output to second delay circuit 64B and second NAM circuit 62.
Second delay circuit 64B delays mixed signal Ye by one half period of CCD output signal Ya and outputs signal Yf shown in FIG. 11(f) to second NAM circuit 62. With mixed signal Ye and delay signal Yf input, second NAM circuit 62 selects a higher level signal between mixed signal Ye and delay signal Yf, during any of reset-level period r, feedthrough-level period T, and signal-level period v of CCD output signal Ya. Therefore, mixed signal Yg, which second NAM circuit 62 outputs, has a waveform shown in FIG. 11(g).
A waveform of mixed signal Yg includes a high level part of mixed signal Ye and a high level part of delay signal Yf.
LPF 67 receives mixed signal Yg from second NAM circuit 62, rejects useless high frequencies, makes the signal smoothed, and outputs final output signal Yh shown in FIG. 11(h).
With a number of pixels of CCD increased and with a period during which a signal for one pixel is processed (hereinafter referred to as pixel period) decreased, the noise reduction circuit which employs the delay and differential noise suppression method shown in FIG. 8 needs to a broadband switching circuit used in gate circuit 58. Therefore, the noise reduction circuit hardly gets enough noise reduction effect.
On the other hand, the noise reduction method for which a NAM circuit is used can surely get enough noise reduction even with CCD of more pixel number and with broader-band noise reduction circuit, because the method does not require a switching operation.
Because an increase in the number of pixels of CCD makes any noise reduction circuit described above needs broadband circuits, the power consumption of the circuit is increased. Namely, the increase in the number of pixels of CCD 50 and 60 makes the pixel period decreased, and makes a signal amplitude at reset-level period r shown in FIG. 9(a) and FIG. 11(a) increased. Therefore, peak-to-peak value A of CCD output signal is increased.
As is clear from the cases of FIG. 9(c) and FIG. 11(c), difference circuit 56 and 66, which are used in conventional noise reduction circuits, must have a wider dynamic range than what is twice as large as peak-to-peak value A. Therefore, the power consumption of the difference circuits is increased. Likewise, gate circuit 58 and first and second NAM circuits in later stages of difference circuits 56 and 66 must have a wider dynamic range than what is twice as large as peak-to-peak value A. Therefore, the power consumption of these circuits is increased. Furthermore, since pulse generator 65 shown in FIG. 10 has to generate pulse signal Yd with a large peak-to-peak value, the power consumption of the generator is increased.